
M1010-01 Datasheet Rev 0.4
M1010-01 VCSO Based Clock Jitter Attenuator
Revised 29Sep2003
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M1010-01
VCSO B
ASED
C
LOCK
J
ITTER
A
TTENUATOR
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n
G
ENERAL
D
ESCRIPTION
The M1010-01 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for OC-12 and OC-48 optical
network systems supporting 622 -
2,488 MHz rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1010-01 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
F
EATURES
◆
Ideal for OC-12/48 data clock
◆
Integrated SAW delay line
◆
Output frequencies from 150 to 175 MHz
(Specify VCSO output frequency at time of order)
◆
Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)
◆
LVPECL clock output
◆
Pin-selectable feedback and reference divider ratios,
no programming required
◆
Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
S
IMPLIFIED
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using
M1010-01-155.5200
Input Reference
Frequency
Input (Mfin)
Ratio
Clock
(MHz)
19.44
77.76
155.52
Output
Clock MHz
8
2
1
155.52
Table 1: Example I/O Clock Frequency Combinations
M1010
(Top View)
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
F
G
N
D
n
R
D
n
V
VCC
NC
nFOUT
FOUT
GND
NC
NC
VCC
GND
FIN_SEL0
SEL0
SEL1
SEL2
NC
VCC
DNC
DNC
DNC
n
O
V
n
n
O
G
G
G
1
2
2
2
2
2
2
2
2
R Div
VCSO
Mfin Div
M Div
Divider LUT
Mfin Divider
LUT
FIN_SEL1:0
REF_SEL
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
0
1
M1010
FOUT
nFOUT
SEL2:0
3
2
Loop
Filter