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參數(shù)資料
| 型號(hào)： | M1021-12I173.3708LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 440K |
| 代理商： | M1021-12I173.3708LF |
M1020/21 Datasheet Rev 1.0
M1020/21 VCSO Based Clock PLL
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
● www.icst.com
●
tel (508) 852-5400
M1020/21
VCSO B
ASED
C
LOCK
PLL
Integrated
Circuit
Systems, Inc.
P r o d u c t D a t a S h e e t
G
ENERAL
D
ESCRIPTION
The M1020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
F
EATURES
◆
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (
LOL
) output pin
◆
Narrow Bandwidth control input (
NBW
pin)
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) / SDH
(G.813) MTIE and TDEV compliance during reselection
◆
Pin-selectable feedback and reference divider ratios
◆
Industrial temperature grade available
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
S
IMPLIFIED
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using
M1020-11-155.5200 or M1021-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
(M1020) (M1021)
19.44 or 38.88
77.76
155.52
622.08
(M1020) (M1021)
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
M1020
M1021
(Top View)
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
M
G
N
D
n
R
D
n
V
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
n
O
V
n
n
O
G
G
G
1
2
2
2
2
2
2
2
2
M1020/21
Phase
Detector
FOUT0
nFOUT0
MR_SEL3:0
R Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
1
P_SEL1:0
LOL
VCSO
Loop
TriState
FOUT1
nFOUT1
P Divider
LUT
M Divider
NBW
2
P Divider
(1, 2, or TriState)
4
M/R Divider
LUT
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| M1021-12I173.3708 | ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 |
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