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參數資料
| 型號： | M1034-16I156.2500 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1034 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 200K |
| 代理商： | M1034-16I156.2500 |
M1033/34 Preliminary Information 0.1
Revised 07Apr2005
Integr a t ed Cir cui t S ystems , Inc . ● N e tw or kin g & C o mm un icat ion s ● www. icst.com ● te l (5 08 ) 85 2-5 4 0 0
M1033/34
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Integrated
Circuit
Systems, Inc.
Prelimina r y Inf o r m ation
GENERAL DESCRIPTION
The M1033/34 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1033/34 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FEATURES
◆ Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆ Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Loss of Reference (LOR) output pin; Narrow Bandwidth
control input (NBW pin)
◆ AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆ Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆ Phase Build-out only upon MUX reselection option
(PBOM)
◆ Pin-selectable feedback and reference divider ratios
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using M1033-11-155.5200 or M1034-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
(M1033)
(M1034)
19.44 or 38.88
(M1033)
(M1034)
8 or 4
155.52
or
77.76
2
155.52
1
622.08
0.25
Table 1: Example I/O Clock Frequency Combinations
M 1 033
M 1 034
( T op V i ew )
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
MR
_
SEL3
GN
D
NC
D
IF_
REF0
nD
IF
_
R
EF0
R
E
F_
SEL
D
IF_
REF1
nD
IF
_
R
EF1
VC
C
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
MR_SEL2
MR_SEL0
MR_SEL1
LOR
NBW
VCC
DNC
nO
P_IN
OP_OU
T
VC
nVC
nOP_OU
T
OP
_
IN
GN
D
GN
D
GN
D
19
20
21
22
23
24
25
26
27
FOUT
nFOUT
TriState
Loop Filter
PLL
Phase
Detector
P_SEL1:0
NBW
M1033/34
VCSO
P Divider
LUT
M Divider
P Divider
(1, 2, or TriState)
MR_SEL3:0
R Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
M / R Divider
LUT
Auto
Ref Sel
1
0
REF_ACK
AUTO
4
Activity
Detector
DIF_REF1
nDIF_REF1
Activity
Detector
LOR
2
0
1
M1033/34 VCSO Based Clock PLL with AutoSwitch
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