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參數資料
| 型號： | M12S16161A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數： | 1/28頁 |
| 文件大小： | 871K |
| 代理商： | M12S16161A |
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ESMT
M12S16161A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
1/28
SDRAM
512K x 16Bit x 2Banks
FEATURES
z
2.5V power supply
z
LVCMOS compatible with multiplexed address
z
Dual banks operation
z
MRS cycle with address key programs
-
CAS Latency (1, 2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
z
EMRS cycle with address key programs.
z
All inputs are sampled at the positive going edge of the
system clock
z
Burst Read Single-bit Write operation
z
Special Function Support.
-
PASR (Partial Array Self Refresh )
-
TCSR (Temperature compensated Self Refresh)
-
DS (Driver Strength)
z
DQM for masking
z
Auto & self refresh
z
32ms refresh period (2K cycle)
Synchronous DRAM
GENERAL DESCRIPTION
The M12S16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
MAX
Freq.
Part NO.
Interface Package Comments
M12S16161A-10T
M12S16161A-15T
M12S16161A-10TG
M12S16161A-15TG
100MHz
66MHz
100MHz
66MHz
Non-Pb-free
Non-Pb-free
Pb-free
Pb-free
LVCMOS
50
TSOP(II)
PIN CONFIGURATION (TOP VIEW)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
相關PDF資料 |
PDF描述 |
|---|---|
| M12S16161A-10T | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A-10TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A-15T | 512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A-15TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M1300 | Mini size of Discrete semiconductor elements |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M12S16161A_07 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A_0707 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A-10T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12S16161A-10TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
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