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參數資料
| 型號： | M16550 |
| 廠商： | Lineage Power |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收器/傳送器) |
| 中文描述： | 通用異步接收器/發送器（通用異步接收器/傳送器） |
| 文件頁數： | 1/11頁 |
| 文件大小： | 124K |
| 代理商： | M16550 |
Features
-
Single-chip synchronous UART in a ORCA 2TA or 3T FPGA
-
Functionally based on the National Semiconductor Corporation NS16550 device
-
Designed to be included in high-speed and high-performance applications
-
System clock up to 85 MHz
-
CPU independent interface
-
Complete asynchronous communication protocol including :
- 5,6,7 or 8-bit data transmission
- Even/Odd or no parity bit generation and detection
- Start and Stop bit generation and detection
- Line break generation and detection
- Receiver Overrun and framing detection
- Up to 1M baud (system frequency dependent)
-
1 to 65535 divisor generates 16X clock
-
Buffered transmit and receive registers
-
Transmitter and receiver are buffered with 16 Byte FIFO, plus 3 error bits per data byte on receiver
-
Polled or interrupt mode
-
Loopback mode
General Description
The macro M16550, based on an ORCA FPGA, implements a synchronous universal asynchronous receiver/transmitter,
which provides an interface between a microprocessor and a serial communication channel.
This macro can be customized according to specific needs (microprocessor and application-specific requirement).
The arbiter and decoding logic can be integrated into the FPGA in addition to any other pre-designed functions.
FPGA density and I/O requirements can be defined according to customer specification.
Summary
Device Family
PFUs
I/O
System Clock
2TA
127 *
27 **
3T
61 *
27 **
-5
: up to 58 MHz
-6
: up to 75 MHz
-7
: up to 85 MHz
-5
: up to 46 MHz
-6
: up to 58 MHz
-7
: up to 74 MHz
Documentation
VHDL Source code
VHDL Test Bench
for behavioral and gate level simulation.
Data Sheet
Design Document
:
features, architecture, interfaces and operation.
User’s guide :
simulation, synthesis and Place and Route procedures.
.prf file
VHDL synthesis Leonardo Spectrum from Exemplar.
VHDL simulation tool.
ORCA Foundry from Lucent.
Support provided by Logic Design Solutions: 90-day e-mail and telephone support
included in the Macro price. Support does not cover user Macro modifications.
Maintenance Contracts are also available.
*
Can change according Software revision, Input flip-flop used on 3T Series.
**
Assuming all Macro signals are routed off-chip.
Constraint Files
Design Tool Requirement
Support
Data Sheet
Aug. 99 –
Ver. 2
M16550
Universal Asynchronous Receiver / Transmitter
MACRO
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