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參數資料
| 型號： | M2004-31I622.0800LF |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 459K |
| 代理商： | M2004-31I622.0800LF |
Preliminar y Inf o r m ation
M2004-x1 Datasheet Rev 1.1
Revised 16Jul2003
Integ r ated Circuit Systems , Inc. ● Comm unications Modules ● www.icst.com ● tel (508) 852-5400
M2004-x1
FREQUENCY TRANSLATION PLL SERIES
GENERAL DESCRIPTION
The M2004 variants -21, -31, -41, and -51 are VCSO
(Voltage Controlled SAW Oscillator)
based clock generator PLLs
designed for clock frequency
translation and jitter attenuation in
a high-speed data communications
system. The clock multiplication ratio
and output divider ratio are pin selectable and also
configurable through serial programming. External loop
components allow the tailoring of PLL loop response.
Based on the M2004-01, these device variants add the
Hitless Switching with Phase Build-out (HS/PBO)
feature. HS/PBO ensures that reference clock
reselection does not disrupt the output clock. In
addition, a fixed Narrow Loop Bandwidth feature (Fixed
NBW) is included in all but the M2004-41.
FEATURES
◆ Pin-compatible with M2004-02/-12, these new product
variants offer new functions
◆ Hitless Switching with Phase Build-out to ensure
SONET/SDH MTIE and TDEV compliance during
reference clock reselection
◆ Fixed Narrow Loop Bandwidth feature available
◆ Ideal for OC-48/192 data clock
◆ Integrated SAW (surface acoustic wave) delay line
◆ VCSO frequency from 300 to 700MHz **
◆ Low phase jitter of < 0.5ps rms, typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable or serially programmed configuration
◆ Reference clock inputs support single-ended
LVCMOS, LVTTL
◆ Industrial temperature available
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
* This sheet covers only parts numbered M2004-21, -31, -41, -51.
See M2004-01/-11 Product Data Sheet for M2004-01 & M2004-11.
** Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example Input / Output Frequency Combinations
Input (MHz) VCSO ** (MHz) Output (MHz)
Application
19.44
622.08
77.76
OC-12 / 48
/192
77.76
311.04
155.52
622.08
Device Variants and Corresponding Functions
Variant
Hitless Switching /
Phase Build-out Triggered by
Fixed
NBW
Phase Transient Mux Reselection
M2004-01
no
M2004-11
Yes
no
M2004-21
no
Yes
M2004-31
Yes
M2004-41
no
Yes
no
M2004-51
no
Yes
6
M5:0
N1:0
2
MR
M2004-x1 Frequency Translation PLL Series
*
相關PDF資料 |
PDF描述 |
|---|---|
| M2004-21I622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-51-622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-21-622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-31I622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-21I622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
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