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參數資料
| 型號： | M2006-02I-669.6429 |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 365K |
| 代理商： | M2006-02I-669.6429 |
M2006-02 Datasheet Rev 1.0
Revised 13Jul2004
Integr a t ed Cir cui t S ystems , Inc . ● N e tw or kin g & C o mm un icat ion s ● www. icst.com ● te l (5 08 ) 85 2-5 4 0 0
M2006-02
VCSO BASED FEC CLOCK PLL
Product Data Sheet
GENERAL DESCRIPTION
The M2006-02 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
The device supports both forward
and inverse FEC (Forward Error
Correction) clock multiplication
ratios. Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
◆ Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation, including:
255/238 (OTU1) Mapping and 238/255 De-mapping
255/237 (OTU2) Mapping and 237/255 De-mapping
255/236 (OTU3) Mapping and 236/255 De-mapping
◆ Supports input reference and VCSO frequencies up to
700MHz, supports loop timing modes
(Specify VCSO frequency at time of order)
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Supports active switching between inverse-FEC and
non-FEC clock ratios (same VCSO center frequency)
◆ Ideal for complex ratio FEC ratio translation* and
for use with an unstable reference** (i.e., similar to the
M2006-12 - and pin-compatible - but without the Hitless
Switching and Phase Build-out functions)
◆ Commercial and Industrial temperature grades
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Note *: Complex ratio FEC ratio translation typically results in
low phase detector frequencies.
Note **: An unstable reference which results in phase detector
jitter beyond 2 ns under normal operating conditions
Example I/O Clock Frequency Combinations
Using M2006-02-622.0800 and Inverse FEC Ratios
FEC PLL Ratio
Mfec / Rfec
Base Input Rate 1
(MHz)
Note 1: Input reference clock can be the base frequency shown
Output Clock
(either output)
MHz
1/1
622.0800
622.08
or
155.52
238/255
666.5143
237/255
669.3266
236/255
672.1627
P0_SEL
P1_SEL
M2006-02
Loop
Filter
M2006-02 VCSO Based FEC Clock PLL
相關PDF資料 |
PDF描述 |
|---|---|
| M2006-02-622.0800LF | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-02I669.6429 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-02I672.1600 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-02-644.5313LF | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-02-670.8386LF | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M2006-03-491.5200 | 功能描述:時鐘合成器/抖動清除器 DOCSIS 2 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006-03-491.5200T | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Multiplier Single T/R 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Multiplier Single 36-Pin CLCC T/R 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Tape and Reel |
| M2006-04-425.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk |
| M2006-04-425.0000T | 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006-04-500.0000 | 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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