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M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date
:
Sep. 2000
Revision
:
1.0
1/14
SRAM
128 K x 16 SRAM
HIGH SPEED CMOS SRAM
FEATURES
ORDERING INFORMATION
Fast access times : 10, 12, and 15ns
Fast
OE
access times : 5, 6, and 7ns
Single +3.3V
±
0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
Easy memory expansive with
CE
and
OE
options
Automatic
CE
power down
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44-pin 400mil SOJ
44-pin 400mil TSOP (TypeII)
PRODUCT NO.
Acess Time
(ns)
PACKING
TYPE
SOJ
M21L216128A-10J
M21L216128A-10T
10
TSOP
M21L216128A-12J
SOJ
M21L216128A-12T
12
TSOP
M21L216128A-15J
SOJ
M21L216128A-15T
15
TSOP
GENERAL DESCRIPTION
The M21L216128A is a high speed, low power
asynchronous SRAM containing 2,097,152 bits and
organized as 131,072 by 16 bits, it is produced by high
performance CMOS process.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable (
CE
), separate byte
enable controls (
LB
and
HE
) and output enable (
OE
) with this
organization.
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CE
DQ1
DQ2
DQ3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
HB
LB
DQ16
DQ15
DQ14
DQ13
GND
VCC
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
DQ4
VCC
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
A4
A3
A2
A1
A0
C E
D Q1
D Q2
D Q3
D Q4
V C C
G N D
DQ 5
DQ 6
DQ 7
DQ 8
W E
A16
A15
A14
A13
A12
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
A5
A6
A7
O E
H B
LB
DQ 16
DQ 15
DQ 14
DQ 13
G N D
V C C
DQ 12
DQ 11
DQ 10
D Q9
N C
A8
A9
A10
A11
N C