- 您現在的位置：買賣IC網 > PDF目錄370825 > M2V12D30TP (Mitsubishi Electric Corporation) 512M Double Data Rate Synchronous DRAM PDF資料下載
參數資料
| 型號： | M2V12D30TP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 512M Double Data Rate Synchronous DRAM |
| 中文描述： | 512M雙數據速率同步DRAM |
| 文件頁數： | 1/38頁 |
| 文件大小： | 754K |
| 代理商： | M2V12D30TP |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
MITSUBISHI
ELECTRIC
-1-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
DESCRIPTION
M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit,
M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and
output data and data strobe are referenced on both edges of CLK. The M2S12D20/30TP achieve
very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
- Commands are entered on each positive CLK edge;
- data and data mask are referenced to both edges of DQS
- 4 bank operations are controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge is controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11-12(x4)/ A0-9,11(x8)
SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
- Low Power for the Self Refresh Current ICC6 :4mA (-75L,-10L)
125MHz
100MHz
-10 / -10L
CL=2.5 *
CL=2 *
133MHz
100MHz
-75 / -75L
Clock Rate
Speed Grade
Operating Frequencies
* CL = CAS(Read) Latency
Contents are subject to change without notice.
相關PDF資料 |
PDF描述 |
|---|---|
| M2V12D30TP-75L | 512M Double Data Rate Synchronous DRAM |
| M2S12D20TP-75L | 512M Double Data Rate Synchronous DRAM |
| M2S12D30TP | 512M Double Data Rate Synchronous DRAM |
| M2S12D30TP-75L | 512M Double Data Rate Synchronous DRAM |
| M2S12D20TP-75 | 128 x 64 pixel format, LED Backlight available |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M2V28D20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D20ATP-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D30ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D30ATP-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D40ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
發布緊急采購，3分鐘左右您將得到回復。