- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370826 > M2V28S20TP-8 (Mitsubishi Electric Corporation) 128M Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | M2V28S20TP-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 128M Synchronous DRAM |
| 中文描述： | 128M的同步DRAM |
| 文件頁數(shù)： | 1/52頁 |
| 文件大小： | 639K |
| 代理商： | M2V28S20TP-8 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Jun. '99
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
1
DESCRIPTION
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as
4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20TP,M2V28S30TP,M2V28S40TP achieves very high speed data rates up to 133MHz, and is
suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3V ±0.3V power supply
- Max. Clock frequency
- PC133(-6) supports x4/x8 only. And does not support Low-Power (L) version.
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40TP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20TP/30TP/40TP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
-6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
ITEM
tCLK
tRAS
M2V28S20/30/40TP
-7
-8
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle Time
(Min.)
Active to Precharge Command Period
Row to Column Delay
Access Time from CLK
Ref/Active Command Period
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
Operation Current
(Max.)
(Single Bank)
Self Refresh Current
(Max.)
10ns
50ns
20ns
6ns
70ns
2mA
10ns
50ns
20ns
6ns
70ns
2mA
V28S20
V28S30
V28S40
-6
7.5ns
45ns
20ns
5.4ns
67.5ns
2mA
130mA
-
120mA
135mA
120mA
135mA
120mA
115mA
115mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2V28S20TP-7 | 128 x 64 pixel format, LED Backlight available |
| M2V28S30TP-7 | 128 x 64 pixel format, LED Backlight available |
| M2V28S40TP-7 | 128 x 64 pixel format, LED Backlight available |
| M2V28S30ATP | 128M Synchronous DRAM |
| M2V28S30ATP-6 | 128M Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V28S30ATP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP-6L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP-7L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。