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參數(shù)資料
| 型號(hào)： | M2VD-2HL |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | MPEG-2 Video Decoder for 1080p Single Stream or 1080i Dual Stream |
| 中文描述： | MPEG - 2視頻解碼器1080單流或1080i雙流 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 172K |
| 代理商： | M2VD-2HL |
M2VD-2HL
MPEG-2 Video Decoder for 1080p Single Stream or 1080i Dual Stream
Silicon Image’s M2VD-2HL* is designed to be used in system-on-a-chip solutions for
DVD and STB/DTV markets. With its extensive set of features M2VD-2HL enables com-
panies to easily provide functions like parallel viewing and recording, picture-in-picture or
simultaneous viewing of several channels in television, PC or other relevant environ-
ments. The M2VD-2HL decoder is optimized to satisfy a wide range of applications and
technologies with optimal performance at lowest possible silicon costs. Its interfaces are
optimized for easy integration into a System-on-Chip architecture using the standard on-
chip bus approach. This dramatically reduces the integration effort and enables fast
time-to-market developments.
Applications
Set-top boxes
Digital TV sets and
IPTV applications
DVD players and
recorders
Portable multimedia
players
Surveillance
Key Features
Supports MPEG-1/2
to 1080p @ 60 fps
Full bit rate support
up to 80 Mbps
Small gate count
reduces chip area
Only one IRQ per
picture to external
host
IP Product Brief
M2VD-2HL
System Diagram
Features
ISO/IEC 13818-2 - MPEG-2 Main Profile @
High Level
ISO/IEC 11172-2 - MPEG-1 constrained
parameter set
Support of all ATSC and DVB HDTV formats
Real-time decoding of multiple streams only
limited by frequency.
Error detection and autonomous error con-
cealment with concealment vectors on slice,
macroblock and block layer
Counter for concealed MBs within a picture
and threshold register which indicates the level
of interrupt generation
Software access to relevant internal registers
and parameter stores to provide the possibility
of a flexible error handling and a robust and
error tolerant decoding control
Decoding of Packetized Elementary Stream
(PES) and Elementary Stream (ES)
Sub-Modules
Count
Gate
Memory
Single-ported
64x32
128x26
32x34
Two ported
2x64x32
2x64x12
96x36
96x64
48x64
200x96
VD Pipeline
69K
VD_M14x4
70K
M2VD-2HL Gate Count and RAM Size Estimation
Gate = 2 Input-NAND equivalent, using TSMC 0.13 μm
process and standard cell libraries
*M2VD-2HL was formerly part of
the sci-worx GmbH product port-
folio. Silicon Image acquired sci-
worx in January 2007.
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