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July 2005
M36LLR8860T1, M36LLR8860D1
M36LLR8860M1, M36LLR8860B1
2 x 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
FEATURES SUMMARY
■
MULTI-CHIP PACKAGE
–
2 dice of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
–
1 die of 64 Mbit (4Mb x16) Pseudo SRAM
■
SUPPLY VOLTAGE
–VDDF1 = VDDF2 = VCCP = VDDQF = 1.7 to
1.95V
–VPP = 9V for fast program (12V tolerant)
■
ELECTRONIC SIGNATURE
–
Manufacturer Code: 20h
–
Top Configuration (Top + Top)
M36LLR8860T1: 880Dh + 880Dh
–
Mixed Configuration (Bottom + Top)
M36LLR8860D1: 880Eh + 880Dh
–
Mixed Configuration (Top + Bottom)
M36LLR8860M1: 880Dh + 880Eh
–
Bottom Configuration (Bottom + Bottom)
M36LLR8860B1: 880Eh + 880Eh
■
PACKAGE
–
Compliant with Lead-Free Soldering
Processes
–
Lead-Free Versions
FLASH MEMORY
■
SYNCHRONOUS / ASYNCHRONOUS READ
–
Synchronous Burst Read mode: 54MHz
–
Asynchronous Page Read mode
–
Random Access: 85ns
■
SYNCHRONOUS BURST READ SUSPEND
■
PROGRAMMING TIME
–
10s typical Word program time using
Buffer Enhanced Factory Program
command
■
MEMORY ORGANIZATION
–
Multiple Bank Memory Array: 16 Mbit
Banks
–
Parameter Blocks (Top or Bottom
location)
■
COMMON FLASH INTERFACE (CFI)
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
Figure 1. Package
■
DUAL OPERATIONS
–
program/erase in one Bank while read in
others
–
No delay between read and write
operations
■
SECURITY
–
64 bit unique device number
–
2112 bit user programmable OTP Cells
■
BLOCK LOCKING
–
All blocks locked at power-up
–
Any combination of blocks can be locked
with zero latency
–WPF for Block Lock-Down
–
Absolute Write Protection with VPPF = VSS
PSRAM
■
ACCESS TIME: 70ns
■
ASYNCHRONOUS PAGE READ
–
Page Size: 16 words
–
Subsequent read within page: 20ns
■
LOW POWER FEATURES
–
Temperature Compensated Refresh
(TCR)
–
Partial Array Refresh (PAR)
–
Deep Power-Down (DPD) Mode
■
SYNCHRONOUS BURST READ/WRITE
LFBGA88 (ZAQ)
8 x 10mm
FBGA
Obsolete
Product(s)
- Obsolete
Product(s)