- 您現在的位置：買賣IC網 > PDF目錄180223 > M5-320/192-12AI (LATTICE SEMICONDUCTOR CORP) Fifth Generation MACH Architecture PDF資料下載
參數資料
| 型號： | M5-320/192-12AI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 12 ns, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁數： | 1/47頁 |
| 文件大小： | 1145K |
| 代理商： | M5-320/192-12AI |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
Publication# 20446
Rev: I
Amendment/0
Issue Date: September 2000
MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
x
High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
x
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
x
Performance features to t system needs
— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
— 182 MHz fCNT
— Four programmable power/speed settings per block
x
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
x
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
x
Advanced E2CMOS process provides high performance, cost effective solutions
x
Supported by ispDesignEXPERT software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 5 devices
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
x
Lattice and Third-party hardware programming support
— LatticePRO software for in-system programmability support on PCs and Automated Test
Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
相關PDF資料 |
PDF描述 |
|---|---|
| M5-384/120-10HC | Fifth Generation MACH Architecture |
| M5-384/120-10HI | Fifth Generation MACH Architecture |
| M5-384/120-12HC | Fifth Generation MACH Architecture |
| M5-384/120-12HI | Fifth Generation MACH Architecture |
| M5-384/120-15HC | Fifth Generation MACH Architecture |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M53-20350HLF | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:High Power Low Cost Inductors |
| M53-20350VLF | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:High Power Low Cost Inductors |
| M53-20351HLF | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:High Power Low Cost Inductors |
| M53-20351VLF | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:High Power Low Cost Inductors |
| M53-20521HLF | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:High Power Low Cost Inductors |
發布緊急采購，3分鐘左右您將得到回復。