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參數(shù)資料
| 型號(hào)： | M5LV-512/120-20YI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 1/42頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CPLD 512MC 120I/O 160PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MACH® 5 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 512 |
| 輸入/輸出數(shù)： | 120 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
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Publication# 20446
Rev: J
Amendment/0
Issue Date: April 2002
MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
◆ High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
◆ Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
◆ Performance features to t system needs
— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
— 182 MHz fCNT
— Four programmable power/speed settings per block
◆ Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
◆ Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
◆ Advanced E2CMOS process provides high performance, cost effective solutions
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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