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參數(shù)資料
型號(hào)： M5M4V64S20ATP-8
廠商： Mitsubishi Electric Corporation
英文描述： 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
中文描述： 64M號(hào)（4銀行甲4194304字× 4位）同步DRAM
文件頁(yè)數(shù)： 1/48頁(yè)
文件大?。?/td> 1097K
代理商： M5M4V64S20ATP-8
M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
DESCRIPTION
The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
M5M4V64S20ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz / 100MHz / 83MHz
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
PRELIMINARY
Some of contents are subject to change without notice.
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-3
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
4
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC (Vref)
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A2
A3
Vdd
Max.
Frequency
CLK Access
Time
M5M4V64S20ATP-8
125MHz
6ns
M5M4V64S20ATP-10
100MHz
8ns
M5M4V64S20ATP-12
83MHz
8ns
1
相關(guān)PDF資料
PDF描述
M5M4V64S20ATP-8A 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8L 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V64S20ATP-8A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S30ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-10L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-12 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
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