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參數資料
| 型號： | M5XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 500 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 312K |
| 代理商： | M5XXLFXI |
MoBL Clock
M200/M500
Two-PLL Programmable Clock Generator for
Portable Applications
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 001-29139 Rev. *A
Revised August 10, 2009
Features
■ Device Operating Voltage Options:
MoBL Clock M200 Family: 1.8V
MoBL Clock M500 Family: 2.5V, 3.0V, or 3.3V
■ Selectable clock output voltages for both MoBL Clock M200
and M500:
1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
■ Fully integrated ultra low power phase-locked loops (PLLs)
■ Input reference clock frequency range: 1–48 MHz
■ Output clock frequency range: 3–50 MHz
■ Three I
2C programmable output clocks
■ Programmable output drive strengths
■ 150 ps typical cycle-to-cycle jitter
■ Optional Spread Spectrum for EMI reduction
■ 16-pin (3x3x0.6 mm) QFN Package
■ Industrial temperature range
Benefits
■ Suitable for cell phone, portable, and consumer electronics
applications
■ Multiple high-performance PLLs allow synthesis of unrelated
frequencies
■ Application compatibility in multiple output voltage levels
■ Optional Spread Spectrum capable PLLs with Lexmark or
Linear profile for maximum EMI reduction
■ PLLs can be programmed for system frequency margin tests
■ Meets critical timing requirements in complex system
designs
■ Individually enable or disable each output using I
2C
■ Ease of output clock selection using programmable crossbar
switches
Logic Block Diagram
PLL1
PLL2
(SS)
Output
Dividers
and
Drive
Strength
Control
Crossbar
Switch
PD#/OE
CLK1
CLK3
CLK2
VDD_CLK1
VDD_CLK3
VDD_CLK2
REF SEL
MUX
and
Control
Logic
I2C
EXCLKIN
SCL
SDA
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