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參數資料
| 型號： | M672-8-AA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 622.08 MHz |
| 文件頁數： | 1/4頁 |
| 文件大小： | 197K |
| 代理商： | M672-8-AA |
Communications Modules
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www.icst.com
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tel (508) 852-5400
M672
VCSO
WITH
S
ELECTABLE
O
UTPUT
F
REQUENCY
D
IVIDER
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n
G
ENERAL
D
ESCRIPTION
The M672 is a Voltage Controlled SAW Oscillator
(VCSO) with a selectable output frequency
divider. The output frequency can be
pin-selected to be either the VCSO
fundamental frequency (Fvcso) or a
fraction of Fvcso (
1
/
8
,
1
/
4
, or
1
/
2
depending
on frequency and order code). Available center
fundamental frequencies for the VCSO are between
125 and 700MHz. Divided
Fvcso frequencies are in the
60 to 175MHz range.
The M672 SAW (surface acoustic
wave) VCO is a high Q frequency source for low-jitter
clock generation. It is well suited for phase-locked loop
implementations, clock and data recovery circuits, and
other timing applications in telecom and optical fiber
networking systems (e.g., SONET/SDH).
F
EATURES
◆
Selectable divider chooses one of two output
frequencies; the Fvcso or its divided output frequency
◆
Low phase jitter 0.2ps rms typical (50kHz to 80MHz)
◆
Differential 3.3V LVPECL output
◆
Single 3.3V power supply
◆
Small 5 x 7.5mm SMT (surface mount) package
P
IN
A
SSIGNMENT
(5 x 7.5mm SMT)
Figure 1: Pin Assignment
Sample of
A
vailable
O
utput Frequencies
B
LOCK
D
IAGRAM
Figure 2: Block Diagram
VCS
O
Center
Fundamental
Frequency
1
(MHz)
Note 1: Specify VCSO center frequency and valid
corresponding P divider value at time of order.
See Ordering Information on pg. 4.
Corresponding
P Divider
1
O
utput Frequency
Selections
(MHz)
622.0800
4
622.0800, 155.5200
622.0800
8
622.0800, 77.7600
311.0400
2
311.0400, 155.5200
155.5200
2
155.5200, 77.7600
Table 1: Sample of Available Output Frequencies
(Top View)
1
2
3
4
5
6
V
P
V
n
G
F
M672
P_SEL
VIN
FOUT
nFOUT
SAW Delay Line
Phase
Shifter
M672
P Divider
P=1 (P_SEL=0)
or
d
(P_SEL=1) *
*
The P divider value
d
(4, 8, or 2) is specified as part
of the order number (format is M672-
d
-
xx
).
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