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參數資料
| 型號： | MACH215-20JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 20 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 1/30頁 |
| 文件大小： | 245K |
| 代理商： | MACH215-20JC |
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Publication# 16751
Rev. E
Amendment/0
Issue Date: May 1995
MACH215-12/15/20
High-Density EE CMOS Programmable Logic
FINAL
COM’L: -12/15/20
IND: -14/18/24
DISTINCTIVE CHARACTERISTICS
s
44 Pins
s
32 Output Macrocells
s
32 Input Macrocells
s
Product terms for:
— Individual flip-flop clock
— Individual asynchronous reset, preset
— Individual output enable
s
12 ns tPD Commercial
14.5 ns tPD Industrial
s
67 MHz fCNT
s
38 Inputs with pull-up resistors
s
32 Outputs
s
64 Flip-flops
s
For asynchronous and synchronous
applications
s
4 “PAL22RA8” blocks with buried macrocells
s
Pin-compatible with MACH110, MACH111,
MACH210, and MACH211
GENERAL DESCRIPTION
The MACH215 is a member of the high-performance
EE CMOS MACH device family. This device has
approximately three times the capability of the popular
PAL20RA10 without loss of speed. This device is
designed for use in asynchronous as well as synchro-
nous applications.
The MACH215 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22RA8” structures complete
with product-term arrays and programmable macro-
cells, individual register control product terms, and input
registers. The switch matrix connects the PAL blocks to
each other and to all input pins, providing a high degree
of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
The MACH215 has two kinds of macrocell: output and
input. The MACH215 output macrocell provides regis-
tered, latched, or combinatorial outputs with program-
mable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type decision can be made by the designer or by the
software. Each macrocell has its own dedicated clock,
asynchronous reset, and asynchronous preset control.
The polarity of the clock signal is programmable. All
output macrocells can be connected to an I/O cell.
The MACH215 has dedicated input macrocells which
provide input registers or latches for synchronizing input
signals and reducing setup time requirements.
Lattice Semiconductor
相關PDF資料 |
PDF描述 |
|---|---|
| MACH111-10JC | High-Performance EE CMOS Programmable Logic |
| MACH111-10JI | High-Performance EE CMOS Programmable Logic |
| MACH111-10VC | High-Performance EE CMOS Programmable Logic |
| MACH111-12JC | High-Performance EE CMOS Programmable Logic |
| MACH111-12JI | High-Performance EE CMOS Programmable Logic |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MACH215-24JI | 制造商:Advanced Micro Devices 功能描述:EE PLD, 24 ns, PQCC44 |
| MACH220-10 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH220-10JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH220-10JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH220-12 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
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