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| 型號(hào)： | MACHLV210-20JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 20 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 1/29頁(yè) |
| 文件大小： | 221K |
| 代理商： | MACHLV210-20JC |
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Publication#
17908
Issue Date:
May 1995
Rev.
D
Amendment
/0
MACHLV210-12/15/20
High Density EE CMOS Programmable Logic
COM’L: -12/15/20
FINAL
IND: -18/24
DISTINCTIVE CHARACTERISTICS
I
Low-voltage operation, 3.3-V JEDEC
compatible
— V
CC
= +3.0 V to +3.6 V
I
< 5 mA standby current
I
Patented design allows minimal standby
current without speed degradation
I
Exclusively designed for 3.3-V applications
I
44 Pins
I
64 Macrocells
I
12 ns t
PD
Commercial
18 ns t
PD
Industrial
I
83.3 MHz f
CNT
I
38 Bus-Friendly Inputs
I
32 Outputs
I
64 Flip-flops; 2 clock choices
I
4 “PAL22V16” blocks with buried macrocells
I
Pin-, function-, and JEDEC-compatible with
MACH210
I
Pin-compatible with MACH110, MACH111,
MACH210, MACH211, and MACH215
GENERAL DESCRIPTION
The MACHLV210 is a member of the high-
performance EE CMOS MACH 2
device family. This
device has approximately six times the logic macrocell
capability of the popular PAL22V10 at an equal speed
with a lower cost per macrocell. It is architecturally
identical to the MACH210, with the addition of I/O
pull-up/pull-down resistors and low-voltage, low-power
operation.
The MACHLV210 provides 3.3-V operation with low-
power CMOS technology. The patented design
allows for minimal standby current without speed
degradation by limiting the leakage current when
signals are not switching. At less than 5 mA maximum
standby current, the MACHLV210 is ideal for low-power
applications.
The MACHLV210 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACHLV210 has two kinds of macrocell: output
and buried. The MACHLV210 output macrocell pro-
vides registered, latched, or combinatorial outputs with
programmable polarity. If a registered configuration is
chosen, the register can be configured as D-type or
T-type to help reduce the number of product terms. The
register type decision can be made by the designer or by
the software. All output macrocells can be connected to
an I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACHLV210 has dedicated buried macrocells
which, in addition to the capabilities of the output
macrocell, also provide input registers or latches for
use in synchronizing signals and reducing setup time
requirements.
Lattice Semiconductor
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