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參數(shù)資料
| 型號(hào)： | MAX5937LCESA+ |
| 廠商： | Maxim Integrated |
| 文件頁(yè)數(shù)： | 19/23頁(yè) |
| 文件大小： | 382K |
| 描述： | IC HOT-SWAP CTRLR -48V 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無(wú) |
| 電源電壓： | -10 V ~ -80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
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-48V Hot-Swap Controllers with V
IN
Step Immunity and No R
SENSE
______________________________________________________________________________________ 19
GATE Output
GATE is a complex output structure and its condition at
any moment is dependent on various timing sequences in
response to multiple inputs. A diode to V
EE
prevents neg-
ative excursions. For positive excursions, the states are:
1) Power-off with 2V clamp.
2) 10& pulldown to V
EE.
a. Continuous during startup delay and during
fault conditions.
b. Pulsed following detected step or OV
condition.
3) Floating with 15V clamp. [Prior to GATE ramp]
4) 47礎(chǔ) current source with 15V clamp. [GATE ramp]
5) Pullup to internal 10V supply with 15V clamp. [Full
enhancement]
Appendix B
Step Monitor Component
Selection Analysis
As mentioned previously in the Selecting Resistor and
Capacitor for Step Monitor section, the AC response
from V
IN
to V
OUT
is dependent on the parasitics of the
load. This is especially true for the load capacitor in
conjunction with the power MOSFETs R
DS(ON)
. The
load capacitor (with parasitic ESR and LSR) and the
power MOSFETs R
DS(ON)
can be modeled as a heavily
damped second-order system. As such, this system
functions as a bandpass filter from V
IN
to V
OUT
limiting
the ability of V
OUT
to follow the V
IN
ramp. STEP_MON
lags the V
IN
ramp with a first-order RC response, while
V
OUT
lags with an overdamped second-order
response.
Given a positive V
IN
ramp with ramp rate of dV/dt, the
approximate response of V
OUT
to V
IN
is:
V
OUT
(t) = (dV/dt) x ?/DIV>
C
x (1-e
(-t / 腖,eqv)
)
+ R
DS(ON)
x I
LOAD
(Equation 1)
where ?/DIV>
C
= C
LOAD
x R
DS(ON)
.
Equation 1 is a simplification for the overdamped sec-
ond-order response of the load to a ramp input, ?/DIV>
C
=
C
LOAD
x R
DS(ON),
and corresponds to the ability of the
load capacitor to transfer dV/dt current to the fully
enhanced power MOSFETs R
DS(ON)
. The equivalent
time constant of the load (?/DIV>
L,eqv
) accounts for the para-
sitic series inductance and resistance of the capacitor
and board interconnect. Determine ?/DIV>
L,eqv
empirically
with a few tests to characterize the load dynamic
response to V
IN
ramps.
Similarly, the response of STEP_MON to a V
IN
ramp is:
V
STEP_MON
(t) = (dV/dt) x ?/DIV>
STEP
x (1-e
(-t / 腟TEP)
)
+ 10礎(chǔ) x R
STEP_MON
(Equation 2)
where ?/DIV>
STEP
= R
STEP_MON
x C
STEP_MON.
For proper step detection, V
STEP_MON
must exceed
STEP
TH
prior to V
OUT
reaching V
SC
or within 1.4ms of
V
OUT
reaching V
CB
(or overall V
IN
ramp rates anticipat-
ed in the application). It is impossible to give a fixed set
of design guidelines that rigidly apply over the wide
array of applications that use the MAX5936/
MAX5937. There are, however, limiting conditions and
recommendations that should be observed.
One limiting condition that must be observed is to ensure
that the STEP_MON time constant, ?/DIV>
STEP
, is not so low
that at the lowest ramp rate, the anticipated STEP
TH
can-
not be obtained. The product (dV/dt) x ?/DIV>
STEP
=
?/DIV>
STEP_MON,MAX
, is the maximum differential voltage at
STEP_MON if the V
IN
ramp were to continue indefinitely.
A related condition is setting the STEP_MON voltage
below STEP
TH
with adequate margin, V
STEP_MON
, to
accommodate the tolerance of both I
STEP_OS
(?%) and
R
STEP_MON
. In determining ?/DIV>
STEP_MON
, use the 9.2礎(chǔ)
limit to ensure sufficient margin with worst-case I
STEP_OS
.
The margin of V
OUT
(with respect to V
SC
and V
CB
) is
set when V
SC
and V
CB
were selected from the three
available ranges. This margin may be lower at one of
the temperature extremes and if so, that value should
be used in the following discussion. These margins will
be called V
CB
and V
SC
and they represent the mini-
mum V
OUT
excursion required to trip the respective
fault. R
STEP_MON
is typically set to 100k& ?%. This
gives a V
STEP_MON
of 0.25V, a worst-case low of
0.16V, and a worst-case high of 0.37V. In finding ?/DIV>
STEP
in the equation below, use V
STEP_MON
= 0.37V to
ensure sufficient margin with worst-case I
STEP_OS
.
To set ?/DIV>
STEP
to block all V
CB
and V
SC
faults for any
ramp rate, find the ratio of V
STEP_MON
to V
CB
and
choose ?/DIV>
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STEP
so:
?/DIV>
STEP
= 1.2 x ?/DIV>
C
x V
STEP_MON
/ V
CB
and since R
STEP_MON
= 100k&:
C
STEP_MON
= ?/DIV>
STEP
/ R
STEP_MON
= ?/DIV>
STEP
/ 100k&
After the first-pass component selection, if sufficient
timing margin exists, it is possible but not necessary to
lower R
STEP
below 100k& to reduce the sensitivity of
STEP_MON to V
IN
noise.
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參數(shù)描述 |
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| MAX5937LCESA+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5937LCESA+T | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5937LCESA-T | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5937LNESA | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5937LNESA+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
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