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參數資料
型號: MAX6604ATA+TW
廠商: Maxim Integrated
文件頁數: 9/15頁
文件大?。?/td> 172K
描述: IC TEMP SENSOR DDR MEMORY 8TDFN
標準包裝: 2,500
功能: 溫度監控系統(傳感器),DIMM DDR 內存
傳感器類型: 內部
感應溫度: -20°C ~ 125°C
精確度: ±3°C(最小值)
輸出類型: 2 線串行,I²C?/SMBUS?
輸出警報:
輸出風扇:
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -20°C ~ 125°C
安裝類型: *
封裝/外殼: *
供應商設備封裝: *
包裝: *
Precision Temperature Monitor for
DDR Memory Modules
_______________________________________________________________________________________   9
Table 4. Configuration Register (Read/Write)
Bit 15   Bit 14   Bit 13   Bit 12   Bit 11   Bit 10    Bit 9    Bit 8    Bit 7    Bit 6    Bit 5    Bit 4    Bit 3    Bit 2    Bit 1    Bit 0
BIT
DEFINITION (DESCRIPTIONS IN BOLD TYPE ARE THE DEFAULT VALUES)
0
EVENT mode
0 = Comparator output mode (default)
1 = Interrupt mode
When either of the lock bits is set, this bit cannot be altered until unlocked.
1
EVENT polarity
0 = Active low (default)
1 = Active high
When either of the lock bits is set, this bit cannot be altered until unlocked.
2
Critical EVENT only
0 = EVENT output on alarm or critical temperature mode (default)
1 = EVENT only if temperature is above the value in the critical temp register
When the alarm window lock bit is set, this bit cannot be altered until unlocked.
3
EVENT output control
0 = EVENT output disabled (default) [Disabled means EVENT remains in an inactive voltage level]
1 = EVENT output enabled
When either of the lock bits is set, this bit cannot be altered until unlocked.
4
EVENT output status (read only)
0 = EVENT output condition is not being asserted by this device
1 = EVENT output is being asserted by this device due to alarm window or critical trip condition
The actual conditions causing an EVENT output can be determined from the temperature register. Interrupt mode can be
cleared by writing to the clear EVENT bit. Writing to this bit has no effect; this bit is not affected by the polarity setting.
5
Clear EVENT (write only)
0 = No effect
1 = Clears active event in interrupt mode. Writing to this register has no effect in comparator mode
When read, this bit always returns to zero.
6
Alarm window lock bit
0 = Alarm trips are not locked and can be altered (default)
1 = Alarm trip register settings cannot be altered
This bit is initially cleared. When set, this bit returns a 1 and remains locked until cleared by the internal power-on reset.
Lock bits and other configuration register bits are updated during the same write; double writes are not necessary.
7
Critical trip lock bit
0 = Critical trip is not locked and can be altered (default)
1 = Critical trip register settings cannot be altered
This bit is initially cleared. When set, this bit returns a 1 and remains locked until cleared by the internal power-on reset.
Lock bits and other configuration register bits are updated during the same write; double writes are not necessary.
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