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參數資料
| 型號： | MB40D001 |
| 廠商： | Fujitsu Limited |
| 英文描述： | D/A Converter for Digital Tuning |
| 中文描述： | D / A轉換為數字調諧 |
| 文件頁數： | 3/17頁 |
| 文件大?。?/td> | 214K |
| 代理商： | MB40D001 |
3
MB40D001
I
PIN DESCRIPTION
*1: Be sure that V
CC
A
≥
V
CC
D, and that V
CC
A
≥
V
DD
.
*2: Do not leave this pin in floating state.
Pin no.
Symbol
Description
1 to 4
AO
1
to AO
4
D/A converter analog output pins (V
DD
-GND output).
(Default state: #00 setting level output)
5 to 12
D
11
/AO
5
to
D
4
/AO
12
I/O expander parallel I/O pins (VccA/GND output 0.5 VccA/0.2 VccA input), also
used as D/A converter analog output pins (V
DD
- GND output).
Pin state is controlled by input data.
See “Data Configuration”. (Default state: Input mode, high-impedance state.)
13
V
DD
*
1
D/A converter reference power supply pin.
14
V
CC
D*
1
MCU interface power supply (Power supply for I/O expander).
15 to 18
D
3
to D
0
I/O expander parallel I/O pins (VccD/GND output 0.5 VccD/0.2VccD input).
Pin state is controlled by input data.
See “Data Configuration”. (Default state: Input mode, high-impedance state.)
19
CLK*
2
Shift clock input pin.
When CS = “L”, SI data is loaded into the shift register at the rise of the shift
clock signal.
20
SI*
2
Data input pin (serial input pin).
Used for 16-bit serial data input.
21
SO
Data output pin (serial output pin).
First-bit (LSB) data from the 16-bit shift register is output in synchronization
with the fall of the shift clock signal. When CS = “H”, this pin is in high
impedance state.
22
CS*
2
Chip select signal input pin.
Input to shift registers is enabled when the CS signal falling edges. Shift register
contents can be executed when the CS signal rising edges.
23
V
CC
A*
1
Analog unit power supply pin (Power supply for the OP amp.).
24
GND
Common GND pin.
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