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DS05-10167-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
2 M
×
8 BIT
FAST PAGE MODE DYNAMIC RAM
MB8117800A-60/-70
CMOS 2,097,152
×
8 Bit Fast Page Mode Dynamic RAM
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DESCRIPTION
The Fujitsu MB8117800A is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 8-bit increments. The MB8117800A features a “fast page” mode of operation whereby high-
speed random access of up to 1,024-bits of data within the same row can be selected. The MB8117800A DRAM
is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB8117800A is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB8117800A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB8117800A are not critical and all inputs are TTL compatible.
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PRODUCT LINE & FEATURES
Parameter
MB8117800A-60
60 ns max.
110 ns min.
30 ns max.
15 ns max.
40 ns min.
715 mW max.
11 mW max. (TTL level) / 5.5 mW max. (CMOS level)
MB8117800A-70
70 ns max.
130 ns min.
35 ns max.
17 ns max.
45 ns min.
660 mW max.
RAS Access Time
Random Cycle Time
Address Access Time
CAS Access Time
Hyper Page Mode Cycle Time
Low Power
Dissipation
Operating Current
Standby Current
2,097,152 words
×
8 bit organization
Silicon gate, CMOS, Advanced Capacitor Cell
All input and output are TTL compatible
2048 refresh cycles every 32.8ms
Self refresh function
Early write or OE controlled write capability
RAS-only, CAS-before-RAS, or Hidden
Refresh
Fast Page Mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
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