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參數資料
| 型號： | MB81ES653225 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Consumer/Embedded Application Specific Memory for SiP |
| 中文描述： | 消費/嵌入式SIP應用程序特定的內存 |
| 文件頁數： | 22/44頁 |
| 文件大小： | 485K |
| 代理商： | MB81ES653225 |
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MB81ES653225-12/-12L
22
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second command
(other
bank)
First command
: Illegal Command
*1 : If t
RP
(Min)
<
CL
×
t
CK
, minimum latency is a sum of (BL
+
CL)
×
t
CK
.
*2 : Assume bank of the object is in Idle state.
*3 : Assume output is in High-Z state.
*4 : t
RRD
(Min) of other bank (second command will be asserted) is satisfied.
*5 : Assume other bank is in active, read or write state.
*6 : Assume t
RAS
(Min) is satisfied.
*7 : Assume other banks are not in READA/WRITA state.
*8 : Assume after the last data have been appeared on DQ.
*9 : If t
RP
(Min)
<
(CL
1)
×
t
CK
, minimum latency is a sum of (BL
+
CL
1)
×
t
CK
.
*10 : Assume no I/O conflict.
MRS
ACTV
*
5
READ
*
5,
*
6
READA
*
5
WRIT
*
5,
*
6
WRITA
PRE
PALL
REF
SELF
BST
MRS
t
RSC
t
RSC
*
7
1
*
7
1
*
7
1
*
7
1
t
RSC
t
RSC
t
RSC
t
RSC
t
RSC
ACTV
*
2
t
RRD
*
6,
*
7
1
*
7
t
RAS
1
READ
*
2,
*
4
1
1
1
*
10
1
*
10
1
*
6
1
*
6
1
1
READA
*
1,
*
2
BL
+
t
RP
*
2,
*
4
1
*
6
1
*
6
1
*
6,
*
10
1
*
6,
*
10
1
*
6
1
*
6
BL
+
t
RP
*
2
BL
+
t
RP
*
2,
*
9
BL
+
t
RP
WRIT
*
2,
*
4
1
1
1
1
1
*
6
1
*
6
t
DPL
1
WRITA
*
2
BL
1
+
t
DAL
*
2,
*
3
t
RP
*
2,
*
4
1
*
6
1
*
6
1
*
6
1
*
6
1
*
6
1
*
6
BL
1
+
t
DAL
*
7
1
*
2
BL
1
+
t
DAL
*
2
t
RP
*
2
BL
1
+
t
DAL
*
2,
*
8
t
RP
PRE
*
2,
*
4
1
*
7
1
*
7
1
*
7
1
*
7
1
*
6,
*
7
1
1
PALL
*
3
t
RP
t
RP
1
1
t
RP
*
8
t
RP
1
REF
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
SELFX
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
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