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參數資料
| 型號： | MB86064 |
| 廠商： | FUJITSU LTD |
| 元件分類： | DAC |
| 英文描述： | Dual 14-bit 1GSa/s DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PBGA120 |
| 封裝： | 12 X 12 MM, PLASTIC, EFBGA-120 |
| 文件頁數： | 3/4頁 |
| 文件大小： | 123K |
| 代理商： | MB86064 |
October 2004 Version 1.1
FME/MS/DAC80/FL/5085
MB86064
Dual 14-bit 1GSa/s DAC
Copyright 2004 Fujitsu Microelectronics Europe GmbH
Production
Page 3 of 4
Disclaimer:
The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Line 3 illustrates a conventional DAC
running at half rate.
Input Data
Unsigned binary data to each DAC core is
input via a dedicated parallel LVDS port. As
with the DAC core, data is latched on every
rising and falling edge of the clock in a
pseudo DDR mode. For synchronisation of
data generator(s) two LVDS clock outputs
and a Loop-Clock facility are provided.
Loop-Clock
Maintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularly
taking into account device-to-device variations. The MB86064 minimises potential problems through
its DDR data interface and by providing a loop-clock facility. The on-chip ‘loop’ consists of an LVDS
input connected to an LVDS output, through a programmable delay stage. This loop-through, and the
associated tracking from the data generating device, should be incorporated in the feedback loop of
a Delay-Locked Loop (DLL) or Phase-Locked Loop (PLL) clock generator, within the data generating
device. This enables the system to compensate for variations in input/output delays in both the data
generating device and the DAC.
Performance Enhancement Features
Each DAC core integrates a number of performance enhancing features. Performance levels now
reach the level sought after for next generation systems and high direct-IF architectures.
Serial Control Interface
A Fujitsu 4-wire serial interface is provided for configuration and control of the DAC. Programmed
data is stored in a number of read/writable registers.
Waveform Memory Module
The MB86064 incorporates a Waveform Memory Module featuring two 16k point on-chip waveform
memories. These allow the DAC cores to be driven with user programmed waveforms without the
need for external high speed, pattern generators.
Development Kit
A comprehensive Development Kit (DK),
DK86064, is available which comprises a
number of modules. A base motherboard
provides an interface to the DAC, Clock and
Data modules. Also included is a PC USB
Interface Lead & Control Software.
For further details, please refer to the
associated documentation.
0
dBFS
Frequency
-6
Target high direct-IF
generating region
Figure 2 Benefits of DAC core architecture to
Sinx/x response
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MB86064_09 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:High-Performance Digital to Analog Converters |
| MB86064PB-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual 14-bit 1GSa/s DAC Development Kit |
| MB86064PB-GE1 | 功能描述:DAC 14BIT 1GSA/S DUAL 12-EFBGA RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 標準包裝:2,400 系列:- 設置時間:- 位數:18 數據接口:串行 轉換器數目:3 電壓電源:模擬和數字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應商設備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數目和類型:* 采樣率（每秒）:* |
| MB86064PB-G-K1E1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:DAC 14BIT 1GSA/S DUAL |
| MB86065 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:High-Performance Digital to Analog Converters |
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