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參數資料
| 型號： | MB86964PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | SHRINK, PLASTIC, QFP-100 |
| 文件頁數： | 1/52頁 |
| 文件大小： | 373K |
| 代理商： | MB86964PFV-G |
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FEATURES
Fully compliant with ISO/ANSI/IEEE 8802-3 specifica-
tions
Provides generic interface to industry-standard micropro-
cessor busses (X86, 680X0 and RISC)
High-performance packet-buffer architecture pipelines
data for highest throughput
On-chip buffer management controls buffer pointers to re-
duce software overhead and improve performance
Hash filter for multicast packet reception
Power down mode to reduce power dissipation in battery-
powered equipment
Two network ports, AUI and 10BASE-T, with automatic
port selection
Integrated pulse shaper and transmit and receive filters for
10BASE-T
Automatic polarity detection and correction on twisted-
pair cable
Selectable 150 and 100 termination for transmitting on
shielded or unshielded twisted-pair cable, respectively
Low-power CMOS technology
Single 5-volt power supply
100-pin plastic shrink quad flat package (SQFP100)
GENERAL DESCRIPTION
The MB86964 is a high-performance, highly integrated single-
chip device that incorporates a network controller with buffer
management, Manchester encoder/decoder, 10BASE-T trans-
ceiver with on-chip transmit and receive filters, and generic bus
interface for industry-standard microprocessor busses. The
MB86964 allows implementation of adapter solutions with a
minimum of additional support chips. Its generic bus interface
makes it ideal for use on daughter and motherboards, as well as
VESA Local Bus (VL Bus). It also can be easily integrated
onto device controller and communication boards as an em-
bedded LAN adapter.
The buffer management architecture of the MB86964 allows
packet data to flow through an external SRAM buffer memory
acting as an elastic buffer. On-chip FIFOs, together with the
SRAM buffer, pipeline both transmit and receive packets
through the system for maximum performance and minimum
overhead to the host microprocessor. All receive and transmit
pointers are managed automatically by the device to reduce
software overhead and increase packet processing speed. The
MB86964’s transmit buffer is programmable as a single
2-kbyte bank or as two banks of 2, 4, or 8 kbytes each. These
buffers can store multiple data packets, allowing the MB86964
to transmit all of them following a single transmit command,
thereby offering greater design flexibility and throughput. A
ring buffer that can be sized from 4 to 30 kbytes, depending on
the size of the SRAM, acts as a large elastic FIFO buffer to cap-
ture the bursts of receive packets.
The MB86964 performs pulse shaping and filtering internally,
which eliminates the need for external filtering components
and reduces overall system cost. The twisted pair interface is
compatible with shielded and unshielded cables and provides
outputs for transmit, collision and link test LED indicators.
The twisted pair receive threshold can be reduced to allow an
extended range between nodes in low-noise environments. Its
wide range of features makes the MB86964 the ideal device for
10BASE-T twisted-pair Ethernet applications.
Possible configurations for the system bus interface include
I/O mapping, memory mapping and DMA access, or a com-
bination of these. With a 20 Mbyte/s bandwidth, the MB86964
system bus interface allows use of full throughput capacity of
its packet-buffering architecture. The MB86964’s bus modes
are programmable, thereby providing 8- or 16-bit data path
width and big or little endian byte-ordering, permitting effi-
cient data interface with most microprocessors and higher-lev-
el protocols.
The MB86964, which is furnished in a space-efficient 100-pin
plastic shrink quad flat package, is fabricated using Fujitsu’s
high-speed, low-power CMOS process.
PIN CONFIGURATION
100
76
26
50
1
25
75
51
100-PIN
SHRINK
QUAD
FLAT PACK
(SQFP)
TOP VIEW
ETHERNET CONTROLLER WITH 10BASE-T TRANSCEIVER
PRELIMINARY DATA SHEET
REVISED NOVEMBER 1997
MB86964
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MB86965 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965BPF-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86967 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
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