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參數資料
| 型號： | MB87L2250 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 消費家電 |
| 英文描述： | MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, FP-208 |
| 文件頁數： | 2/6頁 |
| 文件大小： | 127K |
| 代理商： | MB87L2250 |
MB87L2250 - MPEG2 Decoder
Product Profile
October 1998
Edition 1.1
2
Fujitsu Mikroelektronik GmbH Proprietary Information
Confidential
1.
Chip Architecture
Figure 1 shows the chip architecture of Demultiplexer and Audio/Video Decoder MB87L2250, which is dedicated
for DVB compliant applications (DVB-S, DVB-C, DVB-T).
Figure 1: Block Diagram
SDRAM Interface
Transport
Demultiplexer)
MPEG
Audio
MPEG
Video
Graphics/Video
Controller
(OSD, Teletext)
PAL / NTSC
Encoder
Audio DAC
SDRAM
(16 MBit,
81MHz)
Demodulation
Module
CPU
SparcLite
(optional)
SDRAM
PROM
CE, EE, Flash
IC Card
Interface A/B
I2C
Interface
1 KByte
Instruction
Cache
APLL
CLK81
CLK54
CLK27
MB87L2250
IR
Receiver
DVB
Descrambler
Host
Interface
(optional)
ARC
32 Bit
RISC CPU
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