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參數資料
| 型號： | MB89V201PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit Proprietary Microcontroller |
| 中文描述： | 8-BIT, 12.5 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數： | 17/44頁 |
| 文件大小： | 427K |
| 代理商： | MB89V201PFV |
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MB89202 Series
17
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I-flag :
Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”.
Cleared to “0” at the reset.
IL1, 0 :
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
N-flag : Set to “1” if the MSB becomes to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is cleared to “0”.
Z-flag : Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise.
V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” if the
overflow does not occur.
C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
“0” otherwise. Set to the shift-out value in the case of a shift instruction.
IL1
IL0
Interrupt level
High-low
0
0
1
High
Low
=
no interrupt
0
1
1
0
2
1
1
3
"0"
"0"
"0"
"0"
"0"
"0"
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
RP
Lower OP codes
b0
A7
A6
A5
A4
A3
A2
A1
A0
A15
Generated addresses
A14 A13 A12 A11 A10
A9
A8
Rule for Conversion of Actual Addresses of the General-purpose Register Area
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