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參數資料
| 型號： | MB91F218SPMC-GTE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數： | 1/72頁 |
| 文件大小： | 1895K |
| 代理商： | MB91F218SPMC-GTE1 |
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FUJITSU MICROELECTRONICS
DATA SHEET
Copyright2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.2
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
32-bit Proprietary Microcontroller
CMOS
FR60Lite MB91210 Series
MB91F211B/213A/F213A/F218S/V210
■ DESCRIPTIONS
MB91210 series is Fujitsu Microelectronics's general-purpose 32-bit RISC microcontroller, which is designed for
embedded control applications that require high-speed real-time processing of consumer appliances. This
microcontroller uses FR60Lite as its CPU, compatible with other products in the FR* family.
This series incorporates a built-in UART with LIN function and CAN controller.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
■ FEATURES
FR CPU
32-bit RISC, load/store architecture, 5-stage pipeline
Maximum operating frequency : 40 MHz (Source oscillation is 4 MHz - PLL clock multiplier system)
16-bit fixed length instructions (basic instructions), one instruction per cycle
Memory-memory transfer instructions, bit processing instructions, barrel shift instructions
- Instructions adapted for embedded applications
Function entry/exit instructions, multiple-register load/store instructions
- Instructions supporting high-level language
Register interlock function
- Easier assembler coding enabled
Built-in multiplier supported at the instruction level
- Signed 32-bit multiplication: 5 cycles
- Signed 16-bit multiplication: 3 cycles
Interrupt (PC/PS save) : 6 cycles, 16 priority levels
Harvard architecture allowing program access and data access to be executed simultaneously.
Instruction compatible with the FR family
(Continued)
DS07-16804-3E
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