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參數(shù)資料
型號： MB91F644APMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 1/132頁
文件大小： 3676K
代理商： MB91F644APMC
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.3
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
32-bit Microcontrollers
CMOS
FR80 MB91640A Series
MB91F644A/V650
■ DESCRIPTION
The MB91640A series is a line of Fujitsu Microelectronics microcontrollers based on a 32-bit RISC CPU core that
feature a variety of peripheral functions for embedded applications that demand high-performance and high-speed
CPU processing.
This series is based on the FR80* family CPU and is implemented as a single chip.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
■ FEATURES
FR80 CPU
32-bit RISC, load/store architecture, five-stage pipeline
General-purpose registers : 32-bit
× 16
16-bit fixed-length instructions (basic instructions) : 1 instruction per cycle
Instructions suitable for embedded applications
- Memory-to-memory transfer, bit processing, barrel shift instructions, etc.
- Instruction support for high level languages
Function entry and exit instructions, instructions for register multi-load and multi-store
- Bit search instruction
“1” detection, “0” detection, transition point detection
- Branch instructions with delay slots
Reduced overhead when processing branches
- Register interlock functions
Facilitate coding in assembly language
- Built-in multiplier/instruction-level support
- Signed 32-bit multiplication
: 5 cycles
- Signed 16-bit multiplication
: 3 cycles
- Interrupts (save PC and PS) : 6 cycles, 16 priority levels
- Harvard architecture allowing program access and data access to be executed simultaneously
- Instruction prefetch function has been added with 4 word instruction queue of CPU
(Continued)
DS07-16910-1E
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