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參數資料
型號: MC100E310FNR2G
廠商: ON Semiconductor
文件頁數: 1/8頁
文件大小: 0K
描述: IC CLOCK BUFFER MUX 2:8 28-PLCC
產品變化通告: Dimensional change 21/Oct/2008
標準包裝: 500
系列: 100E
類型: 扇出緩沖器(分配),多路復用器
電路數: 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/是
輸入: ECL,PECL
輸出: ECL,PECL
頻率 - 最大: 900MHz
電源電壓: 4.2 V ~ 5.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應商設備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2009
January, 2009 Rev. 6
1
Publication Order Number:
MC100E310/D
MC100E310
5VECL Low Voltage 2:8
Differential Fanout Buffer
Description
The MC100E310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The E310 offers two selectable clock inputs to allow for
redundant or test clocks to be incorporated into the system clock trees.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 1020 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10 20 ps increase in TPD, so the
relative skew between any two output pairs remains about 25 ns.
For more information on using PECL, designers should refer to
ON Semiconductor Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series Contains Temperature Compensation
Features
Dual Differential Fanout Buffers
200 ps ParttoPart Skew
50 ps OutputtoOutput Skew
28lead PLCC Packaging
Q Output will Default LOW with Inputs Open or at VEE
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; >2 kV,
Machine Model; >200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
Moisture Sensitivity Level: Pb = 1; PbFree = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 212 devices
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
PLCC28
FN SUFFIX
CASE 776
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
MC100E310FNG
AWLYYWW
128
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