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參數(shù)資料
| 型號(hào)： | MC100E451FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK |
| 中文描述： | 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 112K |
| 代理商： | MC100E451FN |
D1
D1
D2
D2
VCCO
D3
D3
D4
D4
D5
D5
VCCO
Q0
LOGIC DIAGRAM
CLK
VBB
CLK
VEE
MR
NC
D0
26
27
28
2
3
4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
Q5
Q4
VCC
Q3
VCCO
Q2
Q1
D0
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
CLK
CLK
MR
VBB
Q0
Q1
Q2
Q3
Q4
Q5
D
R
D
R
D
R
D
R
D
R
D
R
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E451 contains six D-type flip-flops with single-ended
outputs and differential data inputs. The common clock input is also
differential. The registers are triggered by a positive transition of the
positive clock (CLK) input.
A HIGH on the Master Reset (MR) input resets all Q outputs to LOW.
The VBB output is intended for use as a reference voltage for
single-ended reception of ECL signals to that device only. When using for
this purpose, it is recommended that VBB is decoupled to VCC via a
0.01
μ
F capacitor.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
Differential Inputs: Data and Clock
VBB Output
1100MHz Min. Toggle Frequency
Asynchronous Master Reset
Extended 100E VEE Range of – 4.2V to – 5.46V
75k
Input Pulldown Resistors
Pin
Function
D0– D5
D0– D5
CLK
CLK
MR
VBB
Q0– Q5
+Data Input
– Data Input
+Clock Input
– Clock Input
Master Reset Input
VBB Output
Data Outputs
6-BIT D REGISTER
DIFFERENTIAL
DATA AND CLOCK
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
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PDF描述 |
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| MC10E451 | 0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-High Enable 16-SOIC 0 to 85 |
| MC10E451FN | 0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-High Enable 16-SOIC 0 to 85 |
| MC100E452FN | 5-BIT DIFFERENTIAL REGISTER |
| MC10E452 | 0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-High Enable 16-SOIC 0 to 85 |
| MC10E452FN | 0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-High Enable 16-SOIC 0 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100E451FNG | 功能描述:觸發(fā)器 5V ECL 6-Bit Diff Data / Clock RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100E451FNR2 | 功能描述:觸發(fā)器 5V ECL 6-Bit Diff RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100E451FNR2G | 功能描述:觸發(fā)器 5V ECL 6-Bit Diff Data / Clock RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100E452 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:5V ECL 5-Bit Differential Register |
| MC100E452FN | 功能描述:觸發(fā)器 5V ECL 5-Bit Diff RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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