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參數資料
| 型號： | MC100EP016AMNG |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/13頁 |
| 文件大小： | 0K |
| 描述： | IC UP COUNTER 8BIT BINARY 32-QFN |
| 標準包裝： | 74 |
| 系列： | 100EP |
| 邏輯類型： | 二進制計數器 |
| 方向： | 上 |
| 元件數： | 1 |
| 每個元件的位元數： | 8 |
| 復位： | 異步 |
| 計時： | 同步 |
| 計數速率： | 1.4GHz |
| 觸發器類型： | 正，負 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN（5x5） |
| 包裝： | 管件 |
Semiconductor Components Industries, LLC, 2008
March, 2008 - Rev. 9
1
Publication Order Number:
MC100EP016A/D
MC100EP016A
3.3 VECL 8-Bit
Synchronous Binary
Up Counter
Description
The MC100EP016A is a high-speed synchronous, presettable,
cascadeable 8-bit binary counter. Architecture and operation are the
same as the ECLinPS
family MC100E016 with higher operating
speed.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all-one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non-cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
Features
550 ps Typical Propagation Delay
Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
PECL Mode Operating Range: VCC = 3.0 V to 3.6 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -3.6 V
Open Input Default State
Safety Clamp on Clock Inputs
Internal TC Feedback (Gated)
Addition of COUT and COUT
8-Bit
Differential Clock Input
VBB Output
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
Pb-Free Packages are Available
LQFP-32
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
MC100
EP016A
AWLYYWWG
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or
G = Pb-Free Package
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
32
1
MC100
EP016A
AWLYYWW
G
1
QFN32
MN SUFFIX
CASE 488AM
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