參數資料
| 型號： | MC100EP14DTR2 |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/9頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF MUX 2:5 2GHZ 20TSSOP |
| 標準包裝： | 2,500 |
| 系列： | 100EP |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | ECL，HSTL，PECL |
| 輸出： | ECL，PECL |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2010
June, 2010 Rev. 6
1
Publication Order Number:
MC100EP14/D
MC100EP14
3.3V / 5V1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100EP14 is a low skew 1to5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
singleended (if the VBB output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The EP14 specifically guarantees low outputtooutput skew. Optimal
design, layout, and processing minimize skew within a device and from
device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The VBB pin, an internally generated voltage supply, is available to
this device only. For singleended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
400 ps Typical Propagation Delay
100 ps DevicetoDevice Skew
25 ps Within Device Skew
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode:
VCC = 0 V with VEE = 3.0 V to 5.5 V
Open Input Default State
These are PbFree Devices
TSSOP20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
http://onsemi.com
100
EP14
ALYWG
G
1
20
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC100EP14DTR2G | 功能描述:時鐘驅動器及分配 5V ECL/PECL/HST 1:5 Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100EP16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Differential Receiver |
| MC100EP16D | 功能描述:總線收發器 3.3V/5V ECL Diff RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC100EP16DG | 功能描述:總線收發器 3.3V/5V ECL Diff RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC100EP16DR2 | 功能描述:總線收發器 3.3V/5V ECL Diff RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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