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參數(shù)資料
型號: MC100EP35MNR4G
廠商: ON Semiconductor
文件頁數(shù): 1/11頁
文件大?。?/td> 0K
描述: IC FLIP FLOP JK 3.3/5V ECL 8-DFN
標準包裝: 1
系列: 100EP
功能: 復位
類型: JK 型
輸出類型: 差分
元件數(shù): 1
每個元件的位元數(shù): 1
頻率 - 時鐘: 3GHz
延遲時間 - 傳輸: 410ps
觸發(fā)器類型: 正邊沿
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤
包裝: 剪切帶 (CT)
其它名稱: MC100EP35MNR4GOSCT
Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 6
1
Publication Order Number:
MC10EP35/D
MC10EP35, MC100EP35
3.3V / 5VECL JK Flip-Flop
Description
The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flipflop. The J/K data enters the master portion of the
flipflop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation.
Features
410 ps Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at VEE
PbFree Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
H
= MC10
A = Assembly Location
K
= MC100 L
= Wafer Lot
5R = MC10
Y = Year
3M = MC100 W = Work Week
M = Date Code
G
= PbFree Package
ALYWG
G
HP35
ALYWG
G
KP35
MARKING
DIAGRAMS*
SOIC8
D SUFFIX
CASE 751
TSSOP8
DT SUFFIX
CASE 948R
1
8
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
1
8
HEP35
ALYW
G
1
8
KEP35
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
5R
M
G
14
3M
M
G
14
(Note: Microdot may be in either location)
相關PDF資料
PDF描述
MC10EP35DTR2G IC FLIP FLOP JK ECL HS LV 8TSSOP
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