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參數(shù)資料
| 型號： | MC100EP91DW |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator |
| 中文描述： | TRIPLE ECL TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 174K |
| 代理商： | MC100EP91DW |
Semiconductor Components Industries, LLC, 2006
August, 2006
Rev. 1
1
Publication Order Number:
MC100EP91/D
MC100EP91
2.5 V/3.3 V Any Level
Positive Input to
3.3 V/5.5 V NECL Output
Translator
Description
The MC100EP91 is a triple any level positive input to NECL output
translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL,
CML or LVDS signals, and translates them to differential NECL
output signals (
3.0 V /
5.5 V).
To accomplish the level translation the EP91 requires three power
rails. The V
CC
pins should be connected to the positive power supply,
and the V
EE
pin should be connected to the negative power supply.
The GND pins are connected to the system ground plane. Both V
EE
and V
CC
should be bypassed to ground via 0.01 F capacitors.
Under open input conditions, the D input will be biased at V
CC
/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range: V
CC
= 2.375 V to 3.8 V;
V
EE
=
3.0 V to
5.5 V; GND = 0 V
Q Output will Default LOW with Inputs Open or at GND
Pb
Free Packages are Available*
*For additional information on our Pb
Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
SO
20 WB
DW SUFFIX
CASE 751D
1
20
A
WL, L
YY, Y
WW, W = Work Week
G or
= Pb
Free Package
= Assembly Location
= Wafer Lot
= Year
100
EP91
ALYW
1
24
24 PIN QFN
MN SUFFIX
CASE 485L
24
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
20
1
MC100EP91
AWLYYWWG
http://onsemi.com
(Note: Microdot may be in either location)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100EP91DWG | 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator |
| MC100LVEL34 | 3.3V ECL ±2, ±4, ±8 Clock Generation Chip |
| MC100LVEL34_06 | 3.3V ECL ±2, ±4, ±8 Clock Generation Chip |
| MC100LVEL34D | 3.3V ECL ±2, ±4, ±8 Clock Generation Chip |
| MC100LVEL34DG | 3.3V ECL ±2, ±4, ±8 Clock Generation Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP91DWG | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V/5V Triple ECL PECL TO NECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100EP91DWR2 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator |
| MC100EP91DWR2G | 功能描述:轉(zhuǎn)換 - 電壓電平 PECL TO NECL TRNSLTR RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100EP91MN | 制造商:Rochester Electronics LLC 功能描述: 制造商:ON Semiconductor 功能描述: |
| MC100EP91MNG | 功能描述:轉(zhuǎn)換 - 電壓電平 PECL TO NECL TRNSLTR RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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