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參數(shù)資料
型號(hào): MC100EPT20D
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 3.3VLVTTL/LVCMOS to Differential LVPECL Translator
中文描述: TTL/CMOS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO8
封裝: PLASTIC, SOIC-8
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 226K
代理商: MC100EPT20D
MC100ES6210
Rev 3, 02/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage 2.5/3.3 V Differential
ECL/PECL/HSTL Fanout Buffer
The MC100ES6210 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6210
supports various applications that require to distribute precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low clock skew outputs and superior digital
signal characteristics. Target applications for this clock driver is high performance
clock distribution in computing, networking and telecommunication systems.
Features
Dual 1:5 differential clock distribution
30 ps maximum device skew
Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Supports DC to 3 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL compatible differential clock inputs
Single 3.3 V, 3.3 V, 2.5 V or 2.5 V supply
Standard 32 lead LQFP package
Industrial temperature range
Pin and function compatible to the MC100EP210
32-lead Pb-free Package Available
Functional Description
The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The
device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical,
differential ECL/PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals.
If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven
by single-ended ECL/PECL signals utilizing the VBB bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6210 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210.
MC100ES6210
LOW VOLTAGE DUAL
1:5 DIFFERENTIAL PECL/ECL/HSTL
CLOCK FANOUT BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
相關(guān)PDF資料
PDF描述
MC100EPT20DG 3.3VLVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DR2 3.3VLVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DT 3.3VLVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DTG 3.3VLVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DTR2 3.3VLVTTL/LVCMOS to Differential LVPECL Translator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC100EPT20DG 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V TTL/CMOS to Diff PECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
MC100EPT20DG 制造商:ON Semiconductor 功能描述:TRANSLATOR / LOGIC LEVEL CONVERTER IC
MC100EPT20DR2 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V TTL/CMOS to RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
MC100EPT20DR2G 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V TTL/CMOS to Diff PECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
MC100EPT20DT 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V TTL/CMOS to RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
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