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參數(shù)資料
| 型號： | MC100ES6139DTR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 0.65 MM PITCH, TSSOP-20 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 241K |
| 代理商： | MC100ES6139DTR2 |
MC100ES6139
Rev 3, 06/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V ECL/PECL/HSTL/LVDS
÷2/4,
÷4/5/6 Clock Generation Chip
The MC100ES6139 is a low skew
÷2/4, ÷4/5/6 clock generation chip designed
explicitly for low skew clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output edges are all precisely
aligned. The device can be driven by either a differential or single-ended ECL or,
if positive power supplies are used, LVPECL input signals. In addition, by using
the VBB output, a sinusoidal source can be AC coupled into the device. If a single-
ended input is to be used, the VBB output should be connected to the CLK input
and bypassed to ground via a 0.01
F capacitor.
The common enable (EN) is synchronous so that the internal dividers will only
be enabled/disabled when the internal clock is already in the LOW state. This
avoids any chance of generating a runt clock pulse on the internal clock when the
device is enabled/disabled as can happen with an asynchronous control. The
internal enable flip-flop is clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the negative edge of the clock
input.
Upon startup, the internal flip-flops will attain a random state; therefore, for
systems which utilize multiple ES6139s, the master reset (MR) input must be
asserted to ensure synchronization. For systems which only use one ES6139,
the MR pin need not be exercised as the internal divider design ensures
synchronization between the
÷2/4 and the ÷4/5/6 outputs of a single device. All
VCC and VEE pins must be externally connected to power supply to guarantee
proper operation.
The 100ES Series contains temperature compensation.
Features
Maximum Frequency >1.0 GHz Typical
50 ps Output-to-Output Skew
PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V
ECL Mode Operating Range: VCC = 0 V with VEE = –3.135 V to –3.8 V
Open Input Default State
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
VBB Output
LVDS and HSTL Input Compatible
20-Lead Pb-Free Package Available
MC100ES6139
ORDERING INFORMATION
Device
Package
MC100ES6139DT
TSSOP-20
MC100ES6139DTR2
TSSOP-20
MC100ES6139EJ
TSSOP-20 (Pb-Free)
MC100ES6139EJR2
TSSOP-20 (Pb-Free)
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100ES6220TB | 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MC100ES6220TB | 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MC100ES6222TBR2 | 100E SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MC100ES6222TBR2 | 100E SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MC100ES6222TBR2 | 100E SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100ES6139EJ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-4 LVPECL Div. 2/4, Div. 4/5/6 Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100ES6139EJR2 | 功能描述:時(shí)鐘緩沖器 FSL 1-4 LVPECL Div. 2/4, Div. 4/5/6 Cloc RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100ES6210AC | 功能描述:時(shí)鐘緩沖器 FSL 1-5 Dual Diff LVPECL Fanout Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100ES6210ACR2 | 功能描述:時(shí)鐘緩沖器 FSL 1-5 Dual Diff LVPECL Fanout Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MC100ES6210FA | 功能描述:時(shí)鐘緩沖器 Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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