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參數(shù)資料
| 型號(hào)： | MC100LVEL90DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple ECL to PECL Translator |
| 中文描述： | TRIPLE ECL TO PECL TRANSLATOR, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 114K |
| 代理商： | MC100LVEL90DW |
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 1
Motorola, Inc. 1996
7/95
The MC100LVEL/EL90 is a triple ECL to PECL translator. The device
receives either standard or low voltage differential ECL signals and
translates them to either standard or low voltage differential PECL output
signals. The LVEL device can handle the low voltage signals while the EL
device is designed for the standard signals. It is possible to have low
voltage signals on one side and standard signals on the other if the
LVEL90 is used.
500ps Propagation Delays
Fully Differential Design
Supports both Standard and Low Voltage Operation
20–Lead SOIC Packaging
A VBB output is provided for interfacing with single ended ECL signals
at the input. If a single ended input is to be used the VBB output should be
connected to the D input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a 0.01
μ
F
capacitor. The VBB output is designed to act as the switching reference
for the EL90 under single ended input switching conditions, as a result
this pin can only source/sink up to 0.5mA of current.
To accomplish the level translation the EL/LVEL90 requires three
power rails. The VCC supply should be connected to the positive supply,
and the VEE pin should be connected to the negative power supply. The
GND pins as expected are connected to the system ground plain. Both
VEE and VCC should be bypassed to ground via 0.01
μ
F capacitors.
Under open input conditions, the D input will be biased at VEE/2 and
the D input will be pulled to VEE. This condition will force the Q output to a
LOW, ensuring stability.
D2
D1
Logic Diagram and Pinout: 20-Lead SOIC
(Top View)
D1
17
18
16
15
14
13
12
4
3
5
6
7
8
9
Q0
11
10
Q1
Q1
Q2
Q2
VCC
D0
19
20
2
1
VCC
Q0
D0
D2
VCC
VEE
GND
VBB
GND
VBB
ECL
PECL
ECL
PECL
ECL
PECL
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
1
20
PIN NAMES
Function
ECL Inputs
PECL Outputs
ECL Reference Voltage Output
Pins
Dn
Qn
VBB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVEL90DWG | 功能描述:轉(zhuǎn)換 - 電壓電平 -3.3V/-5V Triple ECL to LVPECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100LVEL90DWG | 制造商:ON Semiconductor 功能描述:TRANSLATOR / LOGIC LEVEL CONVERTER IC |
| MC100LVEL90DWR2 | 功能描述:轉(zhuǎn)換 - 電壓電平 -3.3V/-5V Triple RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100LVEL90DWR2G | 功能描述:轉(zhuǎn)換 - 電壓電平 -3.3V/-5V Triple ECL to LVPECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100LVEL91DW | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V/5V Triple RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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