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參數資料
| 型號： | MC10110 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Dual 3-Input/3-Output OR Gate |
| 中文描述： | 雙3-Input/3-Output或門 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 79K |
| 代理商： | MC10110 |
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 7
1
Publication Order Number:
MC10110/D
The ability to control three parallel lines from a single point makes
the MC10110 particularly useful in clock distribution applications
where minimum clock skew is desired. Three VCC pins are provided
and each one should be used.
PD = 80 mW typ/pkg (No Load)
tpd = 2.4 ns typ (All Outputs Loaded)
tr, tf = 2.2 ns typ (20%–80%)
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
VCC1= PIN 1, 15
VCC2= PIN 16
VEE= PIN 8
12
13
14
11
10
9
2
3
4
7
6
5
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10110L
CDIP–16
25 Units / Rail
MC10110P
PDIP–16
25 Units / Rail
MC10110FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
16
1
A
WL = Wafer Lot
YY
= Year
WW = Work Week
= Assembly Location
CDIP–16
L SUFFIX
CASE 620
MC10110L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10101
AWLYYWW
1
1
16
MC10110P
AWLYYWW
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