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參數資料
| 型號： | MC10134P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 |
| 中文描述： | 10K SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 104K |
| 代理商： | MC10134P |
SEMICONDUCTOR TECHNICAL DATA
3–17
REV 5
Motorola, Inc. 1996
3/93
The MC10134 is a dual multiplexer with clocked D type latches. Each latch
may be clocked separately by holding the common clock in the low state, and
using the clock enable inputs for the clocking function. If the common clock is to
be used to clock the latch, the clock enable (CE) inputs must be in the low state.
In this mode, the enable inputs perform the function of controlling the common
clock (CC).
The data select inputs determine which data input is enabled. A high (H)
level on the A0 input enables data input D12 and a low (L) level on the A0 input
enables data input D11. A high (H) level on the A1 input enables data input D22
and a low (L) level on the A1 input enables data input D21.
Any change on the data input will be reflected at the outputs while the clock is
low. The outputs are latched on the positive transition of the clock. While the
clock is in the high state, a change in the information present at the data inputs
will not affect the output information.
PD= 225 mW typ/pkg (No Load)
tpd= 3.0 ns typ
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
11
4
A1
D11
2
Q1
5
D12
CEO
CC
10
7
9
CE1
D21
13
12
D22
3
Q1
15 Q2
14 Q2
6
A0
TRUTH TABLE
A0
D11
L
L
L
H
H
X
H
X
X
X
C
L
L
L
L
H
D12
X
X
L
H
X
Qn+1
L
H
L
H
Qn
C = CE + CC
DIP
PIN ASSIGNMENT
VCC1
Q1
Q1
D11
D12
A0
CC
VEE
VCC2
Q2
Q2
D21
D22
A1
CEO
CE1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
相關PDF資料 |
PDF描述 |
|---|---|
| MC10153FN | Quad Latch |
| MC10153 | Replaced by SN54LS193 : Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CFP -55 to 125 |
| MC10153L | Quad Latch |
| MC10153P | Quad Latch |
| MC10161P | Binary to 1-8 Decoder (Low) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC10135FN | 制造商:ON Semiconductor 功能描述:Flip Flop JK-Master-Slave Type Pos-Edge 1-Element 20-Pin PLLC Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10135FN WAF | 制造商:ON Semiconductor 功能描述: |
| MC10135FNR2 | 制造商:ON Semiconductor 功能描述:Flip Flop JK-Master-Slave Type Pos-Edge 1-Element 20-Pin PLLC T/R |
| MC10135L | 制造商:ON Semiconductor 功能描述:Flip Flop JK-Master-Slave Type Pos-Edge 1-Element 16-Pin CDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10135P | 制造商:ON Semiconductor 功能描述:Flip Flop JK-Master-Slave Type Pos-Edge 1-Element 16-Pin PDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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