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參數資料
| 型號： | MC10153L |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 127K |
| 代理商： | MC10153L |
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 6
1
Publication Order Number:
MC10153/D
MC10153
Quad Latch
The MC10153 is a high speed, low power, MECL quad latch
consisting of four bistable latch circuits with D type inputs and gated
Q outputs. Open emitters allow a large number of outputs to be
wire-ORed together. Latch outputs are gated, allowing direct wiring to
a bus. When the clock is low, outputs will follow D inputs. Information
is latched on positive going transition of the clock. The MC10153
provides the same logic function as the MC10133, except for inversion
of the clock.
PD = 310 mW typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
DIP PIN ASSIGNMENT
VCC1
Q0
D0
CE
G0
Q1
D1
VEE
VCC2
Q3
D3
CC
CE
Q2
G1
D2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
Q0
Q1
Q2
Q3
3
D0
2Q0
5
G0
7
D1
4
CE
13
CC
12
CE
9
D2
14
D3
6Q1
11 Q2
15 Q3
10
G1
TRUTH TABLE
G
C
D
Qn+1
H
X
L
H
X
Qn
L
H
C = CC + CE
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10153L
CDIP–16
25 Units / Rail
MC10153P
PDIP–16
25 Units / Rail
MC10153FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10153L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10153
AWLYYWW
1
16
MC10153P
AWLYYWW
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