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參數(shù)資料
型號(hào): MC10162
廠商: Motorola, Inc.
英文描述: Binary to 1-8 Decoder(High)
中文描述: 二元至1-8解碼器(高)
文件頁(yè)數(shù): 1/4頁(yè)
文件大小: 112K
代理商: MC10162
SEMICONDUCTOR TECHNICAL DATA
3–78
REV 5
Motorola, Inc. 1996
3/93
The MC10162 is designed to convert three lines of input data to a
one–of–eight output. The selected output will be high while all other outputs are
low. The enable inputs, when either or both are high, force all outputs low.
The MC10162 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of the two
enable inputs is used as the data input, while the other is used as a data enable
input.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1 of the MC10161 data sheet.
PD= 315 ns typ/pkg (No Load)
tpd= 4.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
E0 2
E1 15
A 7
B 9
C 14
6 Q0
5 Q1
4 Q2
3 Q3
13 Q4
12 Q5
11 Q6
10 Q7
TRUTH TABLE
INPUTS
OUTPUTS
E0
E1
C
B
A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
X
X
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
DIP
PIN ASSIGNMENT
VCC1
E0
Q3
Q2
Q1
Q0
A
VEE
VCC2
E1
C
Q4
Q5
Q6
Q7
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10162FN Binary to 1-8 Decoder(High)
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MC10164N Dual Monostable Multivibrators With Schmitt-trigger Inputs 16-CDIP -55 to 125
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