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參數資料
| 型號： | MC10319 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hex Inverter Buffers/Drivers With Open-Collector High-Voltage Outputs 14-CDIP -55 to 125 |
| 中文描述： | 高Speed8位模擬數字轉換器 |
| 文件頁數： | 1/20頁 |
| 文件大小： | 338K |
| 代理商： | MC10319 |
Device
Operating
Temperature Range
Package
SEMICONDUCTOR
TECHNICAL DATA
HIGH SPEED
8–BIT ANALOG–TO–DIGITAL
FLASH CONVERTER
ORDERING INFORMATION
MC10319DW
MC10319P
TA = 0
°
to +70
°
C
SO–28L
Plastic
PIN CONNECTIONS
(P only)
Order this document from Analog Marketing
P SUFFIX
PLASTIC PACKAGE
CASE 709
DW SUFFIX
PLASTIC PACKAGE
CASE 751F
(SO–28L)
16
15
17
18
GND
VCC(D)
D1
D2
D3
D4
12
11
10
9
8
7
VCC(D)
GND
VCC(A)
VIN
VEE
14
13
CLOCK
EN
EN
D0
GND
VRT
VRB
21
19
20
22
24
23
D5
D6
OVER–
RANGE
VRM
GND
4
6
5
D7
3
1
2
1
MOTOROLA ANALOG IC DEVICE DATA
The MC10319 is an 8–bit high speed parallel flash A/D converter. The
device employs an internal Grey Code structure to eliminate large output
errors on fast slewing input signals. It is fully TTL compatible, requiring a
+ 5.0 V supply and a wide tolerance negative supply of – 3.0 to – 6.0 V.
Three–state TTL outputs allow direct drive of a data bus or common I/O
memory.
The MC10319 contains 256 parallel comparators across a precision input
reference network. The comparator outputs are fed to latches and then to an
encoder network, to produce an 8–bit data byte plus an overrange bit. The
data is latched and converted to 3–state LS–TTL outputs. The overrange bit
is always active to allow for either sensing of the overrange condition or ease
of interconnecting a pair of devices to produce a 9–bit A/D converter.
Applications include video display and radar processing, high speed
instrumentation and TV broadcast encoding.
Internal Grey Code for Speed and Accuracy, Binary Outputs
8–Bit Resolution/9–Bit Typical Accuracy
Easily Interconnected for 9–Bit Conversion
3–State LS–TTL Outputs with True/Complement Enable Inputs
25 MHz Sampling Rate
Wide Input Range: 1.0 to 2.0 Vpp, between
±
2.0 V
Low Input Capacitance: 50 pF
Low Power Dissipation: 618 mW
No Sample/Hold Required for Video Bandwidth Signals
Single Clock Cycle Conversion
Representative Block Diagram
(1)
VRB
(23)
(24)
Vin
(14)
(13)
V(15)
Clock
(18)
Bias
MC10319
Bias
256
Comparators
(19)
Enable
D1 (10)
D0 (21)
Differential
Latch
Array
Output
Latches
and
ECL–TTL
Converters
Grey Code
Translator
D6 (5)
D7 (4)
(20)
Enable
D5 (6)
D4 (7)
D2 (9)
D3 (8)
Over–
Range
(3)
Logic
VCC(D)
GND
(2, 12,
16, 22)
Analog
Input
Motorola, Inc. 1996
Rev 0
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