參數資料
| 型號： | MC10E131FNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC FLIP FLOP 4BIT ECL 5V 28PLCC |
| 標準包裝： | 1 |
| 系列： | 10E |
| 功能： | 復位 |
| 類型： | D 型總線 |
| 輸出類型： | 差分 |
| 元件數： | 1 |
| 每個元件的位元數： | 4 |
| 頻率 - 時鐘： | 1.4GHz |
| 延遲時間 - 傳輸： | 500ps |
| 觸發器類型： | 正邊沿 |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC10E131FNR2GOSCT |
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 11
1
Publication Order Number:
MC10E131/D
MC10E131, MC100E131
5VECL 4-Bit D Flip-Flop
Description
The MC10E/100E131 is a quad master-slave D-type flip-flop with
differential outputs. Each flip-flop may be clocked separately by
holding Common Clock (CC) LOW and using the Clock Enable (CE)
inputs for clocking. Common clocking is achieved by holding the CE
inputs LOW and using CC to clock all four flip-flops. In this case, the
CE inputs perform the function of controlling the common clock, to
each flip-flop.
Individual asynchronous resets are provided (R). Asynchronous set
controls (S) are ganged together in pairs, with the pairing chosen to
reflect physical chip symmetry.
Data enters the master when both CC and CE are LOW, and transfers
to the slave when either CC or CE (or both) go HIGH.
The 100 Series contains temperature compensation.
Features
1100 MHz Min. Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Metastability Time Constant is 200 ps.
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
PbFree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 240 devices
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= PbFree Package
PLCC28
FN SUFFIX
CASE 776
MCxxxE131G
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
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