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參數(shù)資料
| 型號： | MC10EL34D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | ±2, ±4, ±8 Clock Generation Chip |
| 中文描述： | 10EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 3 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 94K |
| 代理商： | MC10EL34D |
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 2
Motorola, Inc. 1996
12/93
÷
÷
÷
The MC10/100EL34 is a low skew
÷
2,
÷
4,
÷
8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the VBB output, a sinusoidal
source can be AC coupled into the device (see Interfacing section of the
ECLinPS
Data Book DL140/D). If a single-ended input is to be used, the
VBB output should be connected to the CLK input and bypassed to ground
via a 0.01
μ
F capacitor. The VBB output is designed to act as the switching
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
50ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
75k
Internal Input Pulldown Resistors
>1000V ESD Protection
VCC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q0
Q1
VCC
Q2
15
16
14
13
12
11
10
2
1
3
4
5
6
7
VCC
9
8
Q2
Q0
EN
NC
CLK
CLK
VBB
MR
VEE
D
Q
R
Q
R
÷
2
Q
R
÷
4
Q
R
÷
8
Q1
PIN
FUNCTION
CLK
EN
MR
VBB
Q0
Q1
Q2
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff
÷
2 Outputs
Diff
÷
4 Outputs
Diff
÷
8 Outputs
PIN DESCRIPTION
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
FUNCTION
Divide
Hold Q0–3
Reset Q0–3
FUNCTION TABLE
Z = Low-to-High Transition
ZZ = High-to-Low Transition
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
1
16
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC10EL34DG | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 5V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC10EL34DR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 5V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC10EL34DR2G | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 5V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC10EL35D | 功能描述:觸發(fā)器 5V ECL JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC10EL35DG | 功能描述:觸發(fā)器 5V ECL JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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