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參數資料
型號: MC10EP139DWR2
廠商: ON SEMICONDUCTOR
元件分類: 時鐘及定時
英文描述: 3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip
中文描述: 10E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: PLASTIC, SOIC-20
文件頁數: 1/14頁
文件大?。?/td> 102K
代理商: MC10EP139DWR2
Semiconductor Components Industries, LLC, 2005
February, 2005 Rev. 6
1
Publication Order Number:
MC10EP139/D
MC10EP139, MC100EP139
3.3V / 5VECL
÷
2/4,
÷
4/5/6
Clock Generation Chip
The MC10/100EP139 is a low skew
÷
2/4,
÷
4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or singleended ECL or, if positive power supplies are used,
LVPECL input signals. In addition, by using the V
BB
output, a sinusoidal
source can be AC coupled into the device. If a singleended input is to be
used, the V
BB
output should be connected to the CLK input and bypassed
to ground via a 0.01 F capacitor.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. The internal enable flipflop is clocked on the
falling edge of the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Upon startup, the internal flipflops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the
÷
2/4 and the
÷
4/5/6 outputs of a single device. All V
CC
and V
EE
pins must be
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
Maximum Frequency > 1.0 GHz Typical
50 ps OutputtoOutput Skew
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
V
BB
Output
MARKING
DIAGRAMS*
HEP
KEP
XXX
A
L,WL
Y, YY
W, WW = Work Week
= MC10EP
= MC100EP
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
*For additional marking information, refer to
Application Note AND8002/D.
TSSOP20
DT SUFFIX
CASE 948E
HEP or KEP
139
ALYW
20
1
SOIC20
DW SUFFIX
CASE 751D
1
20
1
20
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
20
1
MCXXXEP139
AWLYYWW
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相關代理商/技術參數
參數描述
MC10EP139DWR2G 功能描述:時鐘發生器及支持產品 3.3V/5V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MC10EP142FA 功能描述:計數器移位寄存器 3.3V/5V ECL 9-Bit RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
MC10EP142FAG 功能描述:計數器移位寄存器 3.3V/5V ECL 9-Bit Shift RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
MC10EP142FAR2 功能描述:計數器移位寄存器 3.3V/5V ECL 9-Bit RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
MC10EP142FAR2G 功能描述:計數器移位寄存器 3.3V/5V ECL 9-Bit Shift RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
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