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參數(shù)資料
型號(hào): MC10EP31MNR4G
廠商: ON Semiconductor
文件頁數(shù): 1/11頁
文件大小: 0K
描述: IC FLIP FLOP ECL SET/RST 8-DFN
標(biāo)準(zhǔn)包裝: 1,000
系列: 10EP
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 1
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 3GHz
延遲時(shí)間 - 傳輸: 340ps
觸發(fā)器類型: 正邊沿
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 10
1
Publication Order Number:
MC10EP31/D
MC10EP31, MC100EP31
3.3V / 5VECL D Flip-Flop
with Set and Reset
Description
The MC10/100EP31 is a D flipflop with set and reset. The device
is pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flipflop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
Features
The 100 Series contains temperature compensation.
340 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 3.0 V to 5.5 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at VEE
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
H
= MC10
K
= MC100
5O = MC10
3J
= MC100
M
= Date Code
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R
ALYWG
G
HP31
ALYWG
G
KP31
1
8
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
1
8
HEP31
ALYW
G
1
8
KEP31
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
5O
M
G
14
3J
M
G
14
(Note: Microdot may be in either location)
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