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參數資料
| 型號： | MC10EPT20MNR4G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V LVTTL/LVCMOS to Differential LVPECL Translator |
| 中文描述： | TTL/CMOS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, DSO8 |
| 封裝： | LEAD FREE, DFN-8 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 149K |
| 代理商： | MC10EPT20MNR4G |
Semiconductor Components Industries, LLC, 2006
December, 2006
Rev. 9
1
Publication Order Number:
MC10EPT20/D
MC10EPT20, MC100EPT20
3.3VLVTTL/LVCMOS to
Differential LVPECL
Translator
The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL
translator. Because PECL (Positive ECL) levels are used, only +3.3 V
and ground are required. The small outline SOIC
8 package and the
single gate of the EPT20 makes it ideal for those applications where
space, performance, and low power are at a premium.
The 100 Series contains temperature compensation.
Features
390 ps Typical Propagation Delay
Maximum Input Clock Frequency > 1 GHz Typical
Operating Range V
CC
= 3.0 V to 3.6 V
with GND = 0 V
PNP TTL Input for Minimal Loading
Q Output will Default HIGH with Input Open
Pb
Free Packages are Available
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
Free Package
H
K
5W
3Q
M
= MC10
= MC100
= MC10
= MC100
= Date Code
MARKING DIAGRAMS*
ALYW
HA20
ALYW
KA20
SO
8
D SUFFIX
CASE 751
TSSOP
8
DT SUFFIX
CASE 948R
1
8
1
8
1
8
*For additional marking information, refer to
Application Note AND8002/D.
1
8
HPT20
ALYW
1
8
KPT20
ALYW
1
8
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
DFN8
MN SUFFIX
CASE 506AA
5
1
4
3
1
4
(Note: Microdot may be in either location)
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