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參數資料
| 型號： | MC10H642FN |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 10H SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 172K |
| 代理商： | MC10H642FN |
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 8
1
Publication Order Number:
MC10H642/D
MC10H642, MC100H642
68030/040 PECL to TTL
Clock Driver
Description
The MC10H/100H642 generates the necessary clocks for the
68030, 68040 and similar microprocessors. It is guaranteed to meet the
clock specifications required by the 68030 and 68040 in terms of
parttopart skew, withinpart skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H642 also uses differential PECL internally to achieve its
superior skew characteristic.
The H642 includes dividebytwo and dividebyfour stages, both
to achieve the necessary duty cycle skew and to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Diagram).
The 10H version is compatible with MECL 10H ECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0 V).
Features
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0 V Supply
PbFree Packages are Available*
Function
Reset(R): LOW on RESET forces all Q outputs LOW.
Select(SEL): LOW selects the ECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H642 also contains circuitry to force a stable input state of the
ECL differential input pair, should both sides be left open. In this Case,
the DE side of the input is pulled LOW, and DE goes HIGH.
Power Up: The device is designed to have positive edges of the ÷2
and ÷4 outputs synchronized at Power Up.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= PbFree Package
PLCC28
FN SUFFIX
CASE 776
MCxxxH642G
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC10H642FNG | 功能描述:時鐘驅動器及分配 BBG ECL/TTL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10H642FNR2 | 功能描述:時鐘驅動器及分配 ECL/TTL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10H642FNR2G | 功能描述:時鐘驅動器及分配 BBG ECL/TTL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10H643FN | 功能描述:轉換 - 電壓電平 5V ECL to TTL 1:8 RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC10H643FNG | 功能描述:轉換 - 電壓電平 5V ECL to TTL 1:8 Clock Driver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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